POERS: a performance-oriented energy reduction scheduling technique for a high-performance MPSoC architecture

Continuous improvements in semiconductor technology are supporting new classes of multi-processor system-on-a-chip (MPSoC) architectures that combine extensive processing logic with high-density memory. Such architectures are generally colled processor-in-memory (PIM) or intelligent memory (I-RAM) and can support high-performance computing by reducing the performance gap between the processor and the memory. The PIM architecture combines various processors in a single chip. These processors are characterized by their computation, memory-access, and power consumption capabilities. Therefore, a novel parallelizing system, SAGE II, has be developed to identify their capabilities and dispatch the most appropriate jobs to them in order to exploit the advantages of PIM architectures. This paper provides a new low-power transformation mechanism, called performance-oriented energy reduction scheduling (POERS), to extend the capability of SAGE II system. It can reduce the energy consumption for the processor-in-memory system without losing execution performance. The detailed POERS transformation technique is presented later. The experimental results of several benchmarks are also discussed.