Test-bed board for 16×64 stereo vision CNN chip

Author

Salerno, Mario ; Sargeni, Pausto ; Bonaiuto, Vincenzo

Author_Institution

Dept. of Electron. Eng., Rome Univ., Italy

fYear

2002

fDate

22-24 Jul 2002

Firstpage

662

Lastpage

667

Abstract

The implementation of an artificial vision algorithm in real time is really attractive in such an application as the field of environment sensing. The SVCNN (stereo vision cellular neural network) chip is an analogue circuit able to compute in real time the Disparity Map from a couple of images by using a stereo visual system algorithm. A "test-bed" board for the 16×64 SVCNN chip is presented in this paper. This board is composed of an analogue processing core implemented by two 16×64 SVCNN chips together with a digital high performance pre-processing unit and a video grabbing section.

Keywords

analogue integrated circuits; cellular neural nets; image processing equipment; neural chips; real-time systems; stereo image processing; Disparity Map; SVCNN chip; analogue circuit; artificial vision algorithm; cellular neural network; digital high performance pre-processing unit; environment sensing; real time; stereo vision CNN chip; stereo visual system algorithm; test-bed; video grabbing section; Analog computers; Cellular neural networks; Computer interfaces; Coupling circuits; Equations; Real time systems; Robots; Stereo vision; Testing; Visual system;

fLanguage

English

Publisher

ieee

Conference_Titel

Cellular Neural Networks and Their Applications, 2002. (CNNA 2002). Proceedings of the 2002 7th IEEE International Workshop on

Print_ISBN

981-238-121-X

Type

conf

DOI

10.1109/CNNA.2002.1035109

Filename

1035109