Title :
FPGA Implementation of Real-Time Edge-Preserving Filter for Video Noise Reduction
Author :
Vinh, Truong Quang ; Park, Ju Hyun ; Kim, Young-Chul ; Hong, Sung Hoon
Author_Institution :
Dept. of Comput. Eng., Chonnam Nat. Univ., Gwangju
Abstract :
In this paper, VLSI architectures and FPGA implementation for edge-preserving filter are presented. We proposed two architectures for edge preserving filter: full parallel pipelined and structure-shared architectures. The edge-preserving filter uses adaptive coefficient mask based on the intensity distance in filter blocks. Compared with the bilateral filter, the proposed edge-preserving filter provides significantly noise reduction. We implement the proposed architecture on Cyclone II EP2C70F896C8 FPGA device from Altera Corp. Our experiments show that the PSNR improvement is up to 5.3 dB for Gaussian noisy images.
Keywords :
VLSI; field programmable gate arrays; filtering theory; image denoising; video signal processing; Altera Corp; Cyclone II EP2C70F896C8 FPGA device; FPGA; Gaussian noisy images; VLSI; adaptive coefficient mask; parallel pipelined architectures; real-time edge-preserving filter; structure-shared architectures; video noise reduction; Computer architecture; Delay; Field programmable gate arrays; Hardware; Noise reduction; Nonlinear filters; Smoothing methods; Throughput; Very large scale integration; Video compression; Bilateral filter; Edge preserving filter; FPGA implementation; Noise reduction; VLSI architecture;
Conference_Titel :
Computer and Electrical Engineering, 2008. ICCEE 2008. International Conference on
Conference_Location :
Phuket
Print_ISBN :
978-0-7695-3504-3
DOI :
10.1109/ICCEE.2008.61
