Low power FIR filter FPGA implementation based on distributed arithmetic and residue number system

Author

Wang, Wei ; Swamy, M.N.S. ; Ahmad, M.O.

Author_Institution

Dept. of Electr. & Comput. Eng., Concordia Univ., Montreal, Que., Canada

Volume

1

fYear

2001

fDate

2001

Firstpage

102

Abstract

In this paper, several low power techniques are proposed for the FPGA implementation of a distributed arithmetic and residue number system-based FIR filter. Two algorithms are proposed to reduce the size of the residue-to-binary converter, which is the crucial part of the system. The area, speed and power consumption of the filter is improved accordingly. Furthermore, a lookup table (LUT) partition technique is presented such that the most frequently accessed locations are stored in a smaller memory. The power consumption of the LUTs is reduced because accesses to smaller LUTs dissipate less power. The implementation results show a 20% power reduction by using the proposed methods

Keywords

FIR filters; digital filters; distributed arithmetic; field programmable gate arrays; low-power electronics; residue number systems; table lookup; LUT partition technique; distributed arithmetic; lookup table partition technique; low power FIR filter implementation; low power FPGA implementation; low power techniques; power consumption reduction; residue number system; residue-to-binary converter; Application specific integrated circuits; Digital arithmetic; Digital signal processing; Dynamic range; Energy consumption; Field programmable gate arrays; Finite impulse response filter; Partitioning algorithms; Signal processing algorithms; Table lookup;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2001. MWSCAS 2001. Proceedings of the 44th IEEE 2001 Midwest Symposium on

Conference_Location

Dayton, OH

Print_ISBN

0-7803-7150-X

Type

conf

DOI

10.1109/MWSCAS.2001.986125

Filename

986125