DocumentCode
2288403
Title
An analog self-calibration algorithm for multi-bit per stage pipelined analog to digital converters
Author
Xia, Huimin ; Hassoun, Michael
Author_Institution
Dept. of Electr. & Comput. Eng., Iowa State Univ., Ames, IA, USA
Volume
1
fYear
2001
fDate
2001
Firstpage
207
Abstract
This paper introduces an analog self-calibration algorithm for multi-bit per stage pipelined ADCs. The algorithm employs a high accuracy DAC to serve as the sub-DAC and to calibrate the error introduced by the sub-ADC, sub-DAC and partial effect of the interstage gain amplifier errors. Simulations of a 10-bit 3-stage pipelined ADC demonstrate that the algorithm dramatically improves the static and dynamic performance of the ADC
Keywords
amplifiers; analogue-digital conversion; calibration; circuit simulation; digital-analogue conversion; error correction; pipeline processing; DAC; analog self calibration algorithm; interstage gain amplifier errors; pipelined ADC; Analog-digital conversion; Calibration; Capacitors; Error correction; High speed optical techniques; Optical amplifiers; Phase measurement; Pipelines; Registers; Throughput;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2001. MWSCAS 2001. Proceedings of the 44th IEEE 2001 Midwest Symposium on
Conference_Location
Dayton, OH
Print_ISBN
0-7803-7150-X
Type
conf
DOI
10.1109/MWSCAS.2001.986150
Filename
986150
Link To Document