Title :
GALS Networks on Chip: A New Solution for Asynchronous Delay-Insensitive Links
Author :
Campobello, G. ; Castano, M. ; Ciofi, C. ; Mangano, D.
Author_Institution :
Dipt. di Fisica della Materia e Tecnologie Fisiche Avanzate, Messina Univ.
Abstract :
In this paper a cost effective solution for asynchronous delay-insensitive on-chip communication is proposed. Our solution is based on the Berger coding scheme and allows to obtain a very low wire overhead. For instance, the results of our evaluation show that a 64-bit link can be built paying a wire overhead of 10% and 30 equivalent two-input gates per wire. As a general rule, when the number of bits to be transmitted increases, the wire overhead decreases and the gate overhead remains almost the same
Keywords :
asynchronous circuits; network interfaces; network-on-chip; 64 bit; Berger coding scheme; GALS networks on chip; asynchronous delay-insensitive links; gate overhead; on-chip communication; wire overhead; Clocks; Costs; Delay effects; Electronic mail; Network-on-a-chip; Proposals; Scalability; Synchronization; System-on-a-chip; Wire;
Conference_Titel :
Design, Automation and Test in Europe, 2006. DATE '06. Proceedings
Conference_Location :
Munich
Print_ISBN :
3-9810801-1-4
DOI :
10.1109/DATE.2006.243842
