An efficient behavioral model for delta-sigma modulators

Author

Wu, Jian-Yi ; Bibyk, Steven B.

Author_Institution

Dept. of Electr. Eng., Ohio State Univ., Columbus, OH, USA

Volume

1

fYear

2001

fDate

2001

Firstpage

227

Abstract

This paper demonstrates an efficient and easily built behavioral model of delta-sigma modulators to fulfil the top-down design procedure for analog circuits. The model can be applied to generate sufficient data as digital input signals for optimizing digital circuits of the decimation stages. The high expandability allows designers to form high-order modulator structures and to add or delete some nonidealities and noise sources in different stages of integrators with consideration of simulation time and accuracy. A 4th-order (MASH 211) delta-sigma modulator is designed with this behavioral model to achieve 320-ksamples/s 14.2-ENOB (effective number of bits) performance

Keywords

circuit CAD; circuit optimisation; circuit simulation; delta-sigma modulation; integrated circuit design; integrated circuit modelling; integrated circuit noise; MASH 211 delta-sigma modulator; analog circuits; behavioral model; decimation stage digital circuit optimization; delta-sigma modulators; digital input signal data; effective number of bits performance; expandability; high-order modulator structures; integrators; model; noise sources; nonidealities; simulation accuracy; simulation time; top-down design procedure; Capacitors; Circuit noise; Circuit simulation; Computational modeling; Delta modulation; MATLAB; Mathematical model; Steady-state; Switches; Switching circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2001. MWSCAS 2001. Proceedings of the 44th IEEE 2001 Midwest Symposium on

Conference_Location

Dayton, OH

Print_ISBN

0-7803-7150-X

Type

conf

DOI

10.1109/MWSCAS.2001.986155

Filename

986155