Flexible MPSoC platform with fast interconnect exploration for optimal system performance for a specific application

One of the key elements in multi-processor systems-on-chip (MPSoC) design is to select the optimal on-chip interconnect architecture, in order to maximize the overall system performance. This paper proposes a flexible MPSoC platform, designed for a target application, which allows customizing the interconnect by selecting various architectures. It allows fast building of executable models from architecture specifications and performance evaluation using the cycle-accurate cosimulation. We experimented a DivX encoder application with three different interconnects: DMS (distributed memory server), AMBA bus and octagon network-on-chip (NoC). The simulation results relative to performance metrics such as, average latency, throughput and execution time allowed to compare these different interconnect architectures, to verify the application real-time constraints and to propose further optimizations