DocumentCode :
2288535
Title :
A fast-lock mixed-mode DLL with wide-range operation and multiphase outputs
Author :
Cheng, Kuo-Hsing ; Lo, Yu-Lung
Author_Institution :
Dept. of Electr. Eng., National Central Univ., Taoyuan
Volume :
2
fYear :
2006
fDate :
6-10 March 2006
Abstract :
This paper describes a fast-lock mixed-mode delay-locked loop (MMDLL) for wide-range operation and multiphase outputs. The architecture of the proposed DLL uses the mixed-mode time-to-digital converter (TDC) scheme for frequency range selector, a start-up circuit and coarse tune circuit to offer the faster lock time. And the multi-controlled delay cell for voltage-controlled delay line (VCDL) was used to provide the wide locked range and low-jitter performance. The charge pump circuit is implemented by digital controlled scheme to reach bandwidth tracking. The chip has been fabricated using the TSMC 0.25-mum single-poly five-metal CMOS process with a 2.5 V power supply voltage. From the measurement results, this DLL can operate correctly when the input clock frequency is changed from 32 to 320 MHz and generate ten-phase clocks within just one clock cycle. Moreover, the proposed DLL can solve the problem of the false locking associated with conventional DLL´s and wide-range operation. At 320 MHz, the measured peak-to-peak jitter and root-mean-squared jitter are 37.2 ps and 2.492 ps, respectively. Furthermore, the locking time is less than 22 clock cycles based on the HSPICE simulation results. The DLL occupies smaller area (0.32times0.22 mm2) and dissipates less power (15 mW) than other wide-range DLL´s (Jung, 2001)
Keywords :
CMOS integrated circuits; clocks; delay lines; delay lock loops; digital control; jitter; mixed analogue-digital integrated circuits; 0.25 micron; 15 mW; 2.492 ps; 2.5 V; 32 to 320 MHz; 37.2 ps; HSPICE simulation; MMDLL; TDC scheme; VCDL; charge pump circuit; coarse tune circuit; digital controlled scheme; fast-lock mixed-mode DLL; fast-lock mixed-mode delay-locked loop; frequency range selector; input clock frequency; mixed-mode time-to-digital converter; multicontrolled delay cell; multiphase outputs; peak-to-peak jitter; root-mean-squared jitter; single-poly five-metal CMOS process; start-up circuit; voltage-controlled delay line; Bandwidth; CMOS process; Charge pumps; Clocks; Delay lines; Digital control; Frequency conversion; Jitter; Tuned circuits; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design, Automation and Test in Europe, 2006. DATE '06. Proceedings
Conference_Location :
Munich
Print_ISBN :
3-9810801-1-4
Type :
conf
DOI :
10.1109/DATE.2006.243870
Filename :
1657135
Link To Document :
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