An efficient method to increase throughput using CFFT

In this paper, a novel approach to develop parallel-pipelined architectures for the Fast Fourier transform (FFT) is introduced. The folding transformation and register minimization techniques are proposed for modeling FFT architectures. Novel parallel-pipelined 8-point radix-2 FFT architecture for the computation of complex valued Fast Fourier transform is obtained. For Complex valued Fast Fourier Transform (CFFT), the proposed architecture takes value of underutilized hardware in the serial architecture to obtain L-parallel architectures not including the increment of hardware complexity by a factor of L. To decrease the hardware complexity, the proposed architecture uses redundancy in the computation of FFT samples. A comparison is shown among the proposed design and the previous architectures.