Abstract :
The H.264/AVC inter-prediction is performed for variable block-size motion estimation (VBSME) such as 16times16, 16times8, 8times16, 8times8, 8times4, 4times8 and 4times4, it cause the high complexity for H.264 motion estimation (ME). This investigation develops an architecture for a combined fast motion estimation algorithm with edge information mode decision (EIMD) and predict hexagon search (PHS). Compared with other popular ME architecture, the proposed architecture has a large search range and low processing frequency. For the general specification of SDTV (720times480) with 4 reference frames, search range 256times256, the proposed architecture needs only 18.66 MHz. For the very high specification of QFHD (3840times2160) with 1 reference frame, search range 256times256, the proposed architecture only requires 112 MHz. The gate count of the proposed architecture is 300 K, and the memory usage is 12.6 KB.
Keywords :
computational geometry; edge detection; image matching; motion estimation; search problems; video coding; H.264 video coding; H.264/AVC inter-prediction; edge information mode decision; fast block matching algorithm; frequency 112 MHz; frequency 18.66 MHz; predict hexagon search; real-time QFHD; reference frame; variable block-size motion estimation; Automatic voltage control; Computer architecture; Frequency; Hardware; IEC; ISO; Motion estimation; Transform coding; Video coding; Video compression; H.264; QFHD; fast block matching algorithm; high efficiency architecture; motion estimation;
