DocumentCode
2289386
Title
A time-efficient dither-injection scheme for pipelined SAR ADC
Author
Wang, Rui ; Chio, U-Fat ; Chan, Chi-Hang ; Ding, Li ; Sin, Sai-Weng ; Seng-Pan, U. ; Wang, ZhiHua ; Martins, Rui Paulo
Author_Institution
Inst. of Microelectron., Tsinghua Univ., Beijing, China
fYear
2011
fDate
6-7 Oct. 2011
Firstpage
9
Lastpage
12
Abstract
This paper presents a time-efficient dither-injection scheme in digital domain for pipelined successive approximation register analog-to-digital converter (SAR ADC). Compared with the conventional dither injection method, the proposed method can achieve faster injection speed and reduce the disturbance during the quantization of the ADC. Only 1 LSB dither injection is discussed in this method. Simulation results show more than 8 times speed improvement comparing to the conventional configuration.
Keywords
analogue-digital conversion; analog-to-digital converter; pipelined SAR ADC; pipelined successive approximation register; time-efficient dither-injection scheme; Adders; CMOS integrated circuits; Delay; Logic gates; Multiplexing; Operational amplifiers; Registers; SAR ADC; digital calibration; dither injection; pipelined;
fLanguage
English
Publisher
ieee
Conference_Titel
Microelectronics and Electronics (PrimeAsia), 2011 Asia Pacific Conference on Postgraduate Research in
Conference_Location
Macau
ISSN
2159-2144
Print_ISBN
978-1-4577-1608-9
Type
conf
DOI
10.1109/PrimeAsia.2011.6075058
Filename
6075058
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