Title :
Bit-flipping BIST
Author :
Wunderlich, H.-J. ; Kiefer, G.
Author_Institution :
Comput. Archit. Lab., Stuttgart Univ., Germany
Abstract :
A scan-based BIST scheme is presented which guarantees complete fault coverage with very low hardware overhead. A probabilistic analysis shows that the output of an LFSR which feeds a scan path has to be modified only at a few bits in order to transform the random patterns into a complete test set. These modifications may be implemented by a bit-flipping function which has the LFSR-state as an input, and flips the value shifted into the scan path at certain times. A procedure is described for synthesizing the additional bit-flipping circuitry, and the experimental results indicate that this mixed-mode BIST scheme requires less hardware for complete fault coverage than all the other scan-based BIST approaches published so far.
Keywords :
built-in self test; circuit testing; logic CAD; logic testing; probability; shift registers; LFSR; bit-flipping BIST; bit-flipping circuit design; bit-flipping function; built in self test; complete fault coverage; linear feedback shift registers; mixed-mode BIST scheme; probabilistic analysis; random patterns; scan path; scan-based BIST scheme; very low hardware overhead; Built-in self-test; Circuit faults; Circuit testing; Clocks; Feeds; Hardware; Logic testing; Pattern analysis; System testing; Test pattern generators;
Conference_Titel :
Computer-Aided Design, 1996. ICCAD-96. Digest of Technical Papers., 1996 IEEE/ACM International Conference on
Conference_Location :
San Jose, CA, USA
Print_ISBN :
0-8186-7597-7
DOI :
10.1109/ICCAD.1996.569803
