Conditional sum block for high sparse adders

Sparse tree adders are used for energy efficient and high speed addition operation in microprocessors. However, when the operand length increases, sparse tree adder will have the problem of fan-out and/or wiring in the carry generation network as in prefix adders. Increase in the sparseness will be a solution for this problem. But, Adders with higher sparseness have high fan-out and complex conditional sum computation blocks, which acts as a bottle neck. This paper presents a modified prefix adder with late carry-in which has less fan-out and can be used as sum computation blocks in sparse adders. Sparse tree adders using the proposed sum computation block and with other existing sum computation blocks have been implemented and compared. The proposed design results in reduced power-delay product and area when compared to existing designs.