Estimation of average energy consumption of ripple-carry adder based on average length carry chains

Author

Montalvo, Luis A. ; Parhi, Keshab K. ; Satyanarayana, Janardhan H.

Author_Institution

Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN, USA

fYear

1996

fDate

30 Oct-1 Nov 1996

Firstpage

189

Lastpage

198

Abstract

We show theoretically that the average energy consumption of a ripple-carry adder is O(W), and the upper bound on the average energy consumption is O(Wlog₂W), where W is the word-length of the operands. Our theoretical analysis is based on a simple state transition diagram (STD) model of a full adder cell and the observations that the average length of a carry propagation chain is v=2, and the average length of the maximum carry chain is v⩽log₂W. To verify our theoretical conclusions, we use the HEAT CAD tool to estimate the average power consumed by the ripple-carry adder for word-lengths 4⩽W⩽64. The experimental results show that, for W⩾16, the error in our theoretical estimations is around 15%

Keywords

CMOS logic circuits; adders; carry logic; circuit CAD; digital arithmetic; graph theory; thermal analysis; CMOS full adder; HEAT CAD tool; average energy consumption; average length; average length carry chains; carry propagation chain; experimental results; full adder cell; maximum carry chain; operands wordlength; ripple-carry adder; state transition diagram; upper bound; Adders; Batteries; Circuit testing; Computer applications; Energy consumption; Estimation theory; High performance computing; Integrated circuit technology; Portable computers; Upper bound;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Signal Processing, IX, 1996., [Workshop on]

Conference_Location

San Francisco, CA

Print_ISBN

0-7803-3134-6

Type

conf

DOI

10.1109/VLSISP.1996.558326

Filename

558326