Implementation, verification and synthesis of the Gigabit Ethernet 1000BASE-T physical coding sublayer

Author

Chew, Shei-Li ; Hassoun, Marwan

Author_Institution

Connectivity Solutions, Texas Instrum., Dallas, TX, USA

Volume

2

fYear

2001

fDate

2001

Firstpage

556

Abstract

IEEE standard 802.3ab 1000BASE-T (Gigabit Ethernet) physical layer standard offers a cost-effective solution that upgrades the existing networks to 1000 Mbps data rates. It provides 1 Gbps Ethernet signal transmission over four pairs of category 5 unshielded twisted pair (UTP) cable using the 5-level coding scheme. The Physical Coding Sublayer (PCS) of this standard was simulated using Verilog HDL and synthesized using Synopsys. Two synthesis techniques, hierarchical optimization and hierarchical-flattening optimization, were chosen to compare the tradeoffs between them. The automation of the synthesis was accomplished with the synthesis script files

Keywords

CMOS digital integrated circuits; VLSI; circuit CAD; circuit optimisation; digital communication; encoding; formal verification; high level synthesis; integrated circuit design; local area networks; telecommunication equipment; telecommunication standards; timing; 1 Gbit/s; 1000BASE-T physical coding sublayer; 5-level coding scheme; Gigabit Ethernet; IEEE standard 802.3ab; Synopsys; Verilog HDL; category 5 unshielded twisted pair cable; hierarchical optimization; hierarchical-flattening optimization; synthesis script files; synthesis techniques; Automation; CMOS process; Ethernet networks; Hardware design languages; Network synthesis; Personal communication networks; Physical layer; Semiconductor device modeling; Signal synthesis; USA Councils;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2001. MWSCAS 2001. Proceedings of the 44th IEEE 2001 Midwest Symposium on

Conference_Location

Dayton, OH

Print_ISBN

0-7803-7150-X

Type

conf

DOI

10.1109/MWSCAS.2001.986252

Filename

986252