Memory efficient LDPC decoder design

Hardware complexity of LDPC decoders, which is caused by storage and processing of massive information, is the major reason that encumbers LDPC codes from widely application. Reducing the quantization word length of decoding information can effectively decrease the hardware complexity. But for the absolute value of information keeps increasing during decoding, short word length with finite quantization ranges will lead to serious saturation errors and damage decoding performance. Two quantization schemes is proposed in this paper to reduce the number of memory bits required by decoder design by using short word length while guarantee bit-error-rate (BER) performance. Results shows that these two quantization schemes can simplify the hardware complexity with very little loss of decoding performance.