Title :
High performance CMOS programmable logic array design
Author :
Kuo, Ko-Chi ; Carlson, Bradley S.
Author_Institution :
Boston Design Center, IBM, Lowell, MA, USA
Abstract :
A high performance CMOS Programmable Logic Array (PLA) circuit implemented by a new circuit technique is presented. The gate outputs are preconditioned to minimize delay using a new clocking scheme and circuit design. A multi-level logic and layout synthesis tool which utilizes the CVTL circuit technique is also presented. We describe the overall design methodology for generating the high performance PLA. The simulated benchmark circuits show that the average power-delay product is 2.1 times smaller than the pseudo-nMOS implementations for 0.25 μm process
Keywords :
CMOS logic circuits; delays; integrated circuit design; logic partitioning; multivalued logic; performance evaluation; programmable logic arrays; 0.25 μm process; CMOS; CVTL circuit; clocking; delay; high performance PLA; layout synthesis tool; multi-level logic; power-delay product; programmable logic array; pseudo-nMOS; simulated benchmark circuits; CMOS logic circuits; Circuit synthesis; Clocks; Delay; Logic circuits; Logic design; Logic gates; MOS devices; Programmable logic arrays; Voltage;
Conference_Titel :
Circuits and Systems, 2001. MWSCAS 2001. Proceedings of the 44th IEEE 2001 Midwest Symposium on
Conference_Location :
Dayton, OH
Print_ISBN :
0-7803-7150-X
DOI :
10.1109/MWSCAS.2001.986255
