Title :
High performance CMOS static logic circuit design
Author :
Kuo, Ko-Chi ; Carlson, Bradley S.
Author_Institution :
Boston Design Center, IBM, Lowell, MA, USA
Abstract :
A high performance CMOS static logic implemented by a new circuit technique is presented. The gate outputs are preconditioned to minimize delay using a new clocking scheme and circuit design. The simulated CLA circuit shows that the average power-delay product is 1.62 times smaller than the static implementations for a 0.25 μm process
Keywords :
CMOS logic circuits; adders; carry logic; delays; logic design; timing; 0.25 micron; CLA circuit; CMOS static logic circuit design; carry-lookahead-adder design; clocking scheme; delay minimisation; high performance static logic; preconditioned gate outputs; static logic gate; CMOS logic circuits; CMOS technology; Circuit synthesis; Clocks; Delay; Logic circuits; Logic design; Logic gates; Pulse inverters; Voltage;
Conference_Titel :
Circuits and Systems, 2001. MWSCAS 2001. Proceedings of the 44th IEEE 2001 Midwest Symposium on
Conference_Location :
Dayton, OH
Print_ISBN :
0-7803-7150-X
DOI :
10.1109/MWSCAS.2001.986262
