Low power radiation tolerant VLSI for advanced spacecraft

Author

Benz, Harry F. ; Gambles, Jody W. ; Whitaker, Sterling R. ; Hass, Kenneth J. ; Maki, Gary K. ; Yeh, Pen-Shu

Author_Institution

NASA Langley Res. Center, Hampton, VA, USA

Volume

5

fYear

2002

fDate

2002

Firstpage

183109

Abstract

The combination of two synergistic VLSI technologies, ultra low power CMOS and radiation tolerant by design, offers an opportunity to provide advanced electronics capabilities for future spacecraft. The 500 mV CMOS process can yield orders of magnitude power reduction compared to current space-flight technologies and the radiation tolerance provides immunity against single event latch-up, good single event upset resistance and total ionizing dose immunity of at least 200 krads(Si). A study based on the EO-1 spacecraft requirements indicates that the use of these technologies could provide spacecraft power savings of 73% and total mass savings of 16%.

Keywords

CMOS digital integrated circuits; VLSI; integrated circuit design; integrated circuit reliability; integrated circuit testing; low-power electronics; radiation hardening (electronics); space vehicle electronics; 200 krad; 500 mV; CULPRiT; EO-1 spacecraft; ULP CMOS; VLSI power reduction; low-power radiation tolerant VLSI; radiation tolerance; radiation tolerant by design technology; single event latch-up immunity; single event upset resistance; space-flight technologies; spacecraft electronics; spacecraft power savings; spacecraft total mass savings; total ionizing dose immunity; ultra low power CMOS process; Aerospace electronics; CMOS technology; Capacitance; Capacitors; Circuits; NASA; Space technology; Space vehicles; Very large scale integration; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Aerospace Conference Proceedings, 2002. IEEE

Print_ISBN

0-7803-7231-X

Type

conf

DOI

10.1109/AERO.2002.1035413

Filename

1035413