Reducing the size of a BDD in the combinational circuit power estimation by using the dynamic size limit

In the probability-based power estimation of combinational circuit we use the BDD to calculate the activity of a signal. The CPU time and memory requirement is highly dependent on the size of a BDD, hence it is very important to reduce its size. To reduce the BDD size, previously a predefined static size limit was often used. However, the static size limit can not support the varying importance of nodes. In this paper, we propose a method called dynamic size limit that changes the size limit dynamically to solve the problem. The experimental results show that the proposed method reduces the size of a BDD by about 20% and the CPU time by about 20% on the average compared to the previous static limit methods