Leakage power and delay analysis of LECTOR based CMOS circuits

Author

Verma, Preeti ; Mishra, R.A.

Author_Institution

Electron. & Commun. Eng. Dept., Motilal Nehru Nat. Inst. of Technol., Allahabad, India

fYear

2011

fDate

15-17 Sept. 2011

Firstpage

260

Lastpage

264

Abstract

In CMOS circuits, scaling of threshold voltage results in increase of sub-threshold leakage current. According to the International Roadmap of Semiconductor (ITRS), leakage is projected to grow exponentially during the next decade. LECTOR is a technique for designing CMOS gates in order to reduce the leakage current without affecting the dynamic power dissipation. This paper presents the analysis for leakage current and propagation delay of the basic CMOS gates viz. NOT, NAND and NOR gates implementing LECTOR technique.

Keywords

CMOS logic circuits; delay circuits; leakage currents; logic design; logic gates; power aware computing; CMOS circuit; CMOS gate design; ITRS; International Roadmap of Semiconductor; LECTOR; NAND gate; NOR gate; NOT gate; delay analysis; leakage current reduction; leakage power; propagation delay; sub-threshold leakage current; threshold voltage scaling; CMOS integrated circuits; CMOS technology; Leakage current; Logic gates; Power dissipation; Threshold voltage; Transistors; Deep submicron; Low power; Sub-threshold leakage current; Threshold voltage; Transistor stacking;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer and Communication Technology (ICCCT), 2011 2nd International Conference on

Conference_Location

Allahabad

Print_ISBN

978-1-4577-1385-9

Type

conf

DOI

10.1109/ICCCT.2011.6075117

Filename

6075117