Design and architecture for a multi-mode pipelined, floating-point adder

Author

Gillam, Kenneth R. ; Jones, Keith R.

Author_Institution

Space Syst. Div., Los Angeles AFB, CA, USA

fYear

1991

fDate

20-24 May 1991

Firstpage

73

Abstract

The authors present the design and architecture of a VLSI floating-point adder (FPA). The multi-mode FPA is capable of both single-precision (32-b) and double-precision (64-b) arithmetic and was developed using CMOS technology. The adder is designed for a 40-MHz clock using a pipelined architecture with a two-cycle latency. Area is minimized as hardware is shared for both single-precision and double-precision operations. Two single-precision operations in parallel are possible providing 80-MFLOPS operation. Double-precision operations yield 40-MFLOPS. With the exception of denormalized number representation, the FPA is fully compliant with the IEEE Standard, for floating-point arithmetic. In addition to floating-point operations, the FPA is capable of performing 32-b integer operations. Five format conversions can be performed by the FPA on the four formats that are supported: single-precision, double-precision, integer and block floating-point

Keywords

CMOS integrated circuits; VLSI; adders; digital arithmetic; pipeline processing; 32 bit; 40 MFLOPS; 40 MHz; 80 MFLOPS; CMOS; IEEE Standard; VLSI floating-point adder; block floating-point; double-precision operations; format conversions; integer mode; multi-mode adder; pipelined architecture; single-precision operations; two-cycle latency; Adders; Arithmetic; CMOS technology; Clocks; Latches; Logic; Pipelines; Space technology; Timing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Aerospace and Electronics Conference, 1991. NAECON 1991., Proceedings of the IEEE 1991 National

Conference_Location

Dayton, OH

Print_ISBN

0-7803-0085-8

Type

conf

DOI

10.1109/NAECON.1991.165725

Filename

165725