Title :
A deep sub-micron SRAM cell design and analysis methodology
Author :
Kang, Dae Woon ; Kim, Yong-Bin
Author_Institution :
Dept. of Electr. & Comput. Eng., Northeastern Univ., Boston, MA, USA
Abstract :
This paper presents a comprehensive SRAM design and diagnosis methodology including optimization paradigms on cell stability test against power supply fluctuations, SRAM access time, bit line voltage switching, and static noise margin analysis of a SRAM cell
Keywords :
SRAM chips; integrated circuit design; integrated circuit noise; integrated circuit testing; access time; bit line voltage switching; deep submicron SRAM cell; design methodology; diagnosis methodology; optimization; power supply fluctuations; stability testing; static noise margin analysis; Design engineering; Design methodology; Fluctuations; Geometry; Power engineering computing; Power supplies; Random access memory; Stability; Testing; Threshold voltage;
Conference_Titel :
Circuits and Systems, 2001. MWSCAS 2001. Proceedings of the 44th IEEE 2001 Midwest Symposium on
Conference_Location :
Dayton, OH
Print_ISBN :
0-7803-7150-X
DOI :
10.1109/MWSCAS.2001.986322
