Extended performance analysis of the time predictable on-demand coherent data cache for multi- and many-core systems

Powerful cache systems are required in multi- and many-core systems in order to provide a suitable performance. Moreover, these caches must provide coherent accesses to shared data. With respect to embedded real-time systems, traditional write-invalidate and write-update coherence protocols hamper a static worst case execution time analysis, since the content and state of a local cache can be modified by other cores. Hence, a meaningful cache analysis is no more possible. In previous work, we introduced the On-Demand Coherent Cache (ODC²) which provides coherent accesses to shared data without any coherence transactions and without modifications of other caches. It allows a tight worst case execution time (WCET) analysis at the expense of a decreased hit rate and an additional write-back procedure. In this work, we briefly describe two versions of the ODC² before we present detailed evaluations of its performance and the cost of time predictability. We quantify the overhead of the writeback procedure of one of ODC²´s variations and we estimate the impact on the hit rate.