Variable length instruction compression on Transport Triggered Architectures

The SRAM memories used for embedded micro-processor devices consume a large portion of the system´s power. The power dissipation of the instruction memory can be limited by using code compression methods, which may require the use of variable length instruction formats in the processor. The power-efficient design of variable length instruction fetch and decode is challenging for static multiple-issue processors, which aim for low power consumption on embedded platforms. The power saved using compression is easily lost on inefficient processor design. We propose an implementation for instruction template -based compression and two instruction fetch alternatives for variable length instruction encoding on Transport Triggered Architecture, a static multiple-issue exposed data path architecture. The compression approach reaches an average program size reduction of 44% at best. We show that the variable length fetch designs are sufficiently low-power oriented for the system to benefit from the code compression, which reduces the program memory size.