Title :
A sampled-data CMOS analog adaptive filter
Author :
Gomez, Gabriel ; Siferd, Raymond
Author_Institution :
Wright State Univ., Dayton, OH, USA
Abstract :
A fully analog sampled-data CMOS adaptive filter realizing the LMS (least mean squared) adaptation on a four-tap FIR (finite impulse response) filter has been fabricated. The system uses clocked CMOS sampled-data storage, four-quadrant CMOS analog multipliers, and CMOS op amp-based arithmetic modules. For achieving higher output sampling rates and for allowing modularity, a parallel architecture has been used, implementing each filter tap separately instead of using a single time-multiplexed processing unit. The prototype chip was fabricated using double-metal double-poly 2-μm CMOS P-well technology, occupying an area of 4.0 mm2 and using ±5-V power supplies
Keywords :
CMOS integrated circuits; adaptive filters; analogue computer circuits; least squares approximations; linear integrated circuits; multiplying circuits; parallel architectures; sampled data systems; 2 micron; CMOS P-well technology; CMOS op amp; FIR; arithmetic modules; double metal double poly technology; finite impulse response filter; four tap filter; four-quadrant CMOS analog multipliers; modularity; parallel architecture; sampled-data CMOS analog adaptive filter; sampled-data storage; Adaptive filters; Arithmetic; CMOS technology; Clocks; Finite impulse response filter; Least squares approximation; Parallel architectures; Power supplies; Prototypes; Sampling methods;
Conference_Titel :
Aerospace and Electronics Conference, 1991. NAECON 1991., Proceedings of the IEEE 1991 National
Conference_Location :
Dayton, OH
Print_ISBN :
0-7803-0085-8
DOI :
10.1109/NAECON.1991.165730
