Multi-FPGA prototyping board issue: the FPGA I/O bottleneck

Multi-FPGA boards are widely used for rapid system prototyping. As the ratio between the logic capacity and the number of I/Os for each FPGA generation is increasing, FPGA I/Os are becoming a scarce resource. In order to resolve pin limitation problem, cut nets are sent between FPGAs in a pipelined way using the Time-Division-Multiplexing technique. The maximum number of cut nets passing through one FPGA I/O is called the TDM ratio. There are three inter-FPGA communication architectures: Logic Multiplexing, ISERDES/OSERDES and Multi-Gigabit Transceiver (MGT). Only Logic Multiplexing and ISERDES/OSERDES are today used for Time-Division-Multiplexing in the multi-FPGA based prototyping. In this paper, the achieved performance of Logic Multiplexing and ISERDES/OSERDES is compared in different TDM ratios and a hybrid multiplexing architecture using both ISERDES/OSERDES and MGT is proposed. Experiments are done in a multi-FPGA board with the testbench LFSR to validate the achieved performance. The results show that even though consuming more FPGA I/Os for data transmission, ISERDES/OSERDES can achieve higher performance than Logic Multiplexing. The proposed architecture can achieve higher performance than ISERDES/OSERDES when the TDM ratio exceeds 54. The maximum gain in performance is about 20%.