DocumentCode :
2291957
Title :
Review of FINFET technology
Author :
Jurczak, M. ; Collaert, N. ; Veloso, A. ; Hoffmann, T. ; Biesemans, S.
Author_Institution :
IMEC vzw, Leuven, Belgium
fYear :
2009
fDate :
5-8 Oct. 2009
Firstpage :
1
Lastpage :
4
Abstract :
In view of the difficulties in planar CMOS transistor scaling to preserve an acceptable gate to channel control FINFET based multi-gate (MuGFET) devices have been proposed as a technology option for replacing the existing technology. The attractiveness of FINFET consists in the realization of self-aligned double-gate devices with a conventional CMOS process. This allows extending the gate scaling beyond the planar transitor limits, maintaining a steep subthreshold slope, better performance with bias voltage scaling and good matching due to low doping concentration in the channel. There are, however, several challenges and roadblocks that FINFET technology has to face to be competitive with other technology options: high access resistance related to the extremely thin body, Vtau setting, implementation of strain boosters and manufacturability related to the non planar process and very tight process control.
Keywords :
MOSFET; CMOS process; MuGFET; NMOS FINFET; PMOS FINFET; access resistance; fin dimensions; multi-gate devices; self-aligned double-gate devices; strain boosters; CMOS process; CMOS technology; Capacitive sensors; Doping; FinFETs; High-K gate dielectrics; Immune system; MOS devices; Process control; Threshold voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
SOI Conference, 2009 IEEE International
Conference_Location :
Foster City, CA
ISSN :
1078-621X
Print_ISBN :
978-1-4244-4256-0
Electronic_ISBN :
1078-621X
Type :
conf
DOI :
10.1109/SOI.2009.5318794
Filename :
5318794
Link To Document :
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