Title :
[Copyright notice]
Abstract :
The following topics are dealt with: electronic design automation for design of silicon on insulator (SOI); silicon-on-glass substrate technology; surface nanopatterning; high-efficiency solar cell; thermal actuation; micromechanical resonators; FinFET technology; source-drain asymmetry; wafer stacking; mechanical memory storage; engineering SOI substrate; thermal sensing performance; DNA hybridization; inertial grade SOI MEMS inertial sensors; transconductance ramp effect; quantum confinement effect; ultra-low-power high-noise-margin logic; deep submicron graded channel MOSFETs; three dimensional integration; platinum silicide metallic source; drain process optimisation; electron tunnelling; doping profiles; double gate Schottky MOSFETs; variable-barrier tunnelling SOI transistor; DRAM memory; electronic design automation flow; and cell based SOI design.
Keywords :
DNA; DRAM chips; MOSFET; doping profiles; micromechanical resonators; microsensors; nanopatterning; optimisation; silicon-on-insulator; solar cells; tunnelling; DNA hybridization; DRAM memory; FinFET technology; cell based SOI design; deep submicron graded channel MOSFET; doping profiles; double gate Schottky MOSFET; drain process optimisation; electron tunnelling; electronic design automation; electronic design automation flow; engineering SOI substrate; high-efficiency solar cell; inertial grade SOI MEMS inertial sensors; mechanical memory storage; micromechanical resonators; platinum silicide metallic source; quantum confinement effect; silicon-on-glass substrate technology; silicon-on-insulator; source-drain asymmetry; surface nanopatterning; thermal actuation; thermal sensing performance; three dimensional integration; transconductance ramp effect; ultralow-power high noise margin logic; variable-barrier tunnelling SOI transistor; wafer stacking;
Conference_Titel :
SOI Conference, 2009 IEEE International
Conference_Location :
Foster City, CA
Print_ISBN :
978-1-4244-4256-0
DOI :
10.1109/SOI.2009.5318796
