Title :
Interconnect yield model for manufacturability prediction in synthesis of standard cell based designs
Author :
Heineken, H.T. ; Maly, W.
Author_Institution :
Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
Abstract :
A sound IC design methodology must be supported by adequate manufacturability assessment tools. These tools should assist a designer in predicting IC manufacturing cost in as early a design stage as possible. In this paper a yield model is proposed that takes as input a standard cell netlist and produces as output a yield estimate without performing placement and routing. This yield model has been successfully used to predict the interconnect yield of standard cell designs that were implemented with two place and route tools. The proposed yield model can be used as a crucial component in the objective function of a circuit synthesis tool as well as in technology mapping optimization.
Keywords :
circuit CAD; circuit optimisation; design for manufacture; integrated circuit design; integrated circuit manufacture; integrated circuit yield; network routing; IC design methodology; circuit synthesis tool; integrated circuit design; interconnect yield model; manufacturability prediction; manufacturing cost; placement; routing; standard cell based designs; standard cell netlist; technology mapping optimization; yield estimate; Circuit synthesis; Costs; Design methodology; Integrated circuit interconnections; Integrated circuit modeling; Integrated circuit synthesis; Predictive models; Semiconductor device modeling; Virtual manufacturing; Yield estimation;
Conference_Titel :
Computer-Aided Design, 1996. ICCAD-96. Digest of Technical Papers., 1996 IEEE/ACM International Conference on
Conference_Location :
San Jose, CA, USA
Print_ISBN :
0-8186-7597-7
DOI :
10.1109/ICCAD.1996.569823
