• DocumentCode
    2293358
  • Title

    A 250 Msample/sec programmable cascaded integrator-comb decimation filter

  • Author

    Kwentus, Alan ; Lee, Owen ; Willson, Alan N., Jr.

  • Author_Institution
    Broadcom Corp., Irvine, CA, USA
  • fYear
    1996
  • fDate
    30 Oct-1 Nov 1996
  • Firstpage
    231
  • Lastpage
    240
  • Abstract
    The implementation of a 250 Msample/sec programmable six-stage cascaded integrator-comb (CIC) decimation filter is described. The prototype IC is implemented using 0.8-μm CMOS and contains 39,890 transistors in a core area of 8.5 mm2. It accommodates programmable power-of-two decimation factors from 2 to 1024 with 16-bit input and output data
  • Keywords
    CMOS digital integrated circuits; FIR filters; cascade networks; digital filters; integrating circuits; programmable filters; 0.8 micron; 16 bit; CMOS IC; core area; input data; output data; programmable FIR filter; programmable cascaded integrator-comb decimation filter; programmable power of two decimation factors; prototype IC; transistors; Baseband; CMOS technology; Digital filters; Finite impulse response filter; Frequency response; Narrowband; Prototypes; Signal processing; Transfer functions; Wideband;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Signal Processing, IX, 1996., [Workshop on]
  • Conference_Location
    San Francisco, CA
  • Print_ISBN
    0-7803-3134-6
  • Type

    conf

  • DOI
    10.1109/VLSISP.1996.558351
  • Filename
    558351
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2293358