Title :
Inaccuracies in power estimation during logic synthesis
Author :
Brand, D. ; Visweswariah, C.
Author_Institution :
IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
Abstract :
This paper studies the confidence with which power can be estimated at various levels of design abstraction. We report the results of experiments designed to evaluate and identify the sources of inaccuracies in gate-level power estimation. In particular, we are interested in power estimation during logic synthesis. Factors that may invalidate or diminish the accuracy of pourer estimates include optimization, technology mapping, transistor sizing, physical design, and choice of input stimuli.
Keywords :
logic CAD; power consumption; design abstraction; gate-level power estimation; logic synthesis; optimization; power estimation; technology mapping; transistor sizing; Circuit simulation; Design optimization; Energy consumption; Hardware; Integrated circuit synthesis; Logic; Manufacturing; Power dissipation; Power measurement; Statistics;
Conference_Titel :
Computer-Aided Design, 1996. ICCAD-96. Digest of Technical Papers., 1996 IEEE/ACM International Conference on
Conference_Location :
San Jose, CA, USA
Print_ISBN :
0-8186-7597-7
DOI :
10.1109/ICCAD.1996.569826
