DocumentCode
2293615
Title
A circuit simulator based on the waveform-relaxation method using selective overlapped partition and classified latencies
Author
Shima, Takeshi ; Kamatani, Yukio
Author_Institution
Toshiba Corp., Kawasaki, Japan
fYear
1988
fDate
7-9 June 1988
Firstpage
1651
Abstract
Several techniques for improving simulation costs in the waveform relaxation method are discussed. In the circuit partitioner field, selective overlapped partition and duplication depth ideas are proposed. For the circuit simulation part, several modifications to the conventional simulator are demonstrated and classified latencies proposed. Experimental simulations are compared with results obtained from SPICE2. The results indicate conclusively that, if the circuit size is over one thousand, SUPER-SPICE is more cost-effective than SPICE2.<>
Keywords
circuit analysis computing; digital simulation; circuit partitioner; circuit simulator; classified latencies; selective overlapped partition; simulation costs; waveform-relaxation method; Circuit simulation; Convergence; Data processing; Delay; Equations; Gaussian processes; Mechanical factors; Relaxation methods; Research and development; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1988., IEEE International Symposium on
Conference_Location
Espoo, Finland
Type
conf
DOI
10.1109/ISCAS.1988.15251
Filename
15251
Link To Document