Title :
High speed data bus macro instruction set architecture
Author :
Prohofsky, Thomas
Author_Institution :
Unisys Corp., St. Paul, MN, USA
Abstract :
Unisys Corporation has developed an input/output (I/O) instruction set architecture (ISA) to accommodate I/O devices in reduced instruction set computing (RISC)-based applications. Control over the linear high speed data bus (HSDB) interface is implemented by control registers, memory resident instructions, and memory maps. Instruction chaining allows for autonomous multiple message transmission in addition to single message-by-message control. Handling data reception is customized by the mapping structure, which incorporates message polling, single and multiple message interrupts, and single and multiple message FIFOs. Control registers provide for transitioning between various modes and states within the I/O interface. By defining network accessible control registers, a method is made available for remote interface control. By combining remote interface control and message mapping, some applications may not require a processor to control each I/O interface
Keywords :
computer interfaces; instruction sets; interrupts; military computing; reduced instruction set computing; storage management; FIFOs; I/O interface; RISC; Unisys Corporation; autonomous multiple message transmission; control registers; instruction chaining; linear high speed data bus; macro instruction set architecture; memory maps; memory resident instructions; message interrupts; message mapping; message polling; reduced instruction set computing; remote interface control; Access protocols; Computer architecture; Control systems; Delay; Instruction sets; Operating systems; Process control; Read-write memory; Reduced instruction set computing; Registers;
Conference_Titel :
Aerospace and Electronics Conference, 1991. NAECON 1991., Proceedings of the IEEE 1991 National
Conference_Location :
Dayton, OH
Print_ISBN :
0-7803-0085-8
DOI :
10.1109/NAECON.1991.165745
