Title :
Unit delay simulation with the inversion algorithm
Author :
Schilp, W.J. ; Maurer, P.M.
Author_Institution :
Dept. of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, USA
Abstract :
The Inversion Algorithm is an event driven algorithm whose performance meets or exceeds that of Levelized Compiled Code simulation, even when the activity rate is unrealistically high. Existing implementations of the Inversion Algorithm are based on the Zero Delay model. This paper extends the algorithm to more realistic timing models. The main problems discussed in this paper are avoiding scheduling conflicts, and minimizing the amount of storage space. These problems are made considerably more difficult by the deletion of NOT gates and the collapsing of various connections. These optimizations transform the simulation into a multi-delay simulation under the transport delay model. A complete solution to the scheduling problem is presented under these conditions.
Keywords :
circuit analysis computing; discrete event simulation; logic CAD; logic circuits; NOT gates; Zero Delay model; event driven algorithm; inversion algorithm; multi-delay simulation; scheduling; scheduling conflicts; storage space; transport delay model; Algorithm design and analysis; Computational modeling; Computer science; Computer simulation; Delay; Discrete event simulation; Hazards; Logic; Runtime; Timing;
Conference_Titel :
Computer-Aided Design, 1996. ICCAD-96. Digest of Technical Papers., 1996 IEEE/ACM International Conference on
Conference_Location :
San Jose, CA, USA
Print_ISBN :
0-8186-7597-7
DOI :
10.1109/ICCAD.1996.569831
