Title :
Latch optimization in circuits generated from high-level descriptions
Author :
Sentovich, E.M. ; Toma, H. ; Berry, G.
Author_Institution :
Centre de Mathematiques Appliquees, Ecole Nat. Superieure des Mines de Paris, Sophia-Antipolis, France
Abstract :
In a gate-level description of a finite state machine (FSM), there is a tradeoff between the number of latches and the size of the logic implementing the next-state and output functions. Typically, an initial implementation is generated via explicit state assignment or translation from a high-level language, and the tradeoff is subsequently only lightly explored. We efficiently explore good latch/logic tradeoffs for large designs generated from high-level specifications. We reduce the number of latches while controlling the logic size. We demonstrate the efficacy of our techniques on some large industrial examples.
Keywords :
finite state machines; logic CAD; explicit state assignment; finite state machine; high-level specifications; latch optimization; latch/logic tradeoffs; tradeoff; Circuits; Delay; Design optimization; Encoding; High level languages; Latches; Logic design; Process design; Size control; State-space methods;
Conference_Titel :
Computer-Aided Design, 1996. ICCAD-96. Digest of Technical Papers., 1996 IEEE/ACM International Conference on
Conference_Location :
San Jose, CA, USA
Print_ISBN :
0-8186-7597-7
DOI :
10.1109/ICCAD.1996.569833