Optimum implementation of a multistage IIR SC bandpass decimator for a voiceband analogue interface system

A novel methodology has been developed for the design of multistage infinite impulse response switched-capacitor decimators with optimum implementation. The approach uses a cascade of only IIR SC decimator building blocks as a means of obtaining minimum-order structures for high selectivity filtering requirements with very large factors of sampling rate reduction. The strategy for reducing the sampling rate is determined in conjunction with the pole-zero pairing to achieve relaxed speed requirements for the operational amplifiers together with reduced capacitance spread and total capacitor area. This is demonstrated for an SC bandpass decimator which virtually eliminates the need for costly on-chip continuous-time filters, thus making it extremely attractive for integrated-circuit implementation.<>