A uniform and reconfigurable framework for the multidimensional Fourier transform

A general design is presented based on reconfiguration and massive parallelism, that is, in the context of the hypercomputer supercomputer, a 9072 processor prototype. It is shown that simulated multidimensional Fourier transform (FT) algorithms on the hypercomputer are fast, achieving optimal space and time complexity even though the approach is uniform and does not incorporate any specific architectural optimizations for the FT. Furthermore, each cell in the design is simple, fine-grain (8-b), and to be implemented with high latency circuits (3M200 ns). These hardware limitations are exploited through massive parallelism at the instruction level and the algorithm level. Through the reconfiguration, specialized computation and communication are addressed, tailoring the degree of both to accommodate each other as well as the FT of different problem sizes and with different space-time constraints