DocumentCode :
2295802
Title :
Planar multiple-valued decision diagrams
Author :
Sasao, Tsutomu ; Butler, Jon T.
Author_Institution :
Dept. of Comput. Sci. & Electron., Kyushu Inst. of Technol., Iizuka, Japan
fYear :
1995
fDate :
23-25 May 1995
Firstpage :
28
Lastpage :
35
Abstract :
In VLSI, crossings occupy space and cause delay. Therefore, there is significant benefit to planar circuits. We propose the use of planar multiple-valued decision diagrams to produce planar multiple-valued circuits. Specifically, we show conditions on 1) threshold functions, 2) symmetric functions, and 3) monotone increasing functions that produce planar decision diagrams. Our results apply to binary functions, as well. For example, we show that all two-valued monotone increasing threshold functions of up to five variables have planar binary decision diagrams
Keywords :
field programmable gate arrays; multivalued logic circuits; programmable logic arrays; threshold logic; binary functions; monotone increasing functions; planar multiple-valued decision diagrams; symmetric functions; threshold functions; Binary decision diagrams; Boolean functions; Computer science; Data structures; Delay; Field programmable gate arrays; Input variables; Logic; Space technology; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Multiple-Valued Logic, 1995. Proceedings., 25th International Symposium on
Conference_Location :
Bloomington, IN
ISSN :
0195-623X
Print_ISBN :
0-8186-7118-1
Type :
conf
DOI :
10.1109/ISMVL.1995.513506
Filename :
513506
Link To Document :
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