Title :
Memory circuits for multiple valued logic voltage signals
Author_Institution :
Dept. of Electr. & Comput. Eng., California Univ., Davis, CA, USA
Abstract :
Voltage-mode CMOS multiple valued logic memory circuits have been realized in a standard 2-micron p-well polysilicon-gate CMOS technology. These circuits requantize multiple-valued logical voltages during a SETUP clock mode and latch the input value during the HOLD clock mode. Using a 5 volt supply and logical voltage increments of 1.67 volts, two similar quaternary memory circuits have worst-case total SETUP and HOLD times of about 5.7 ns and 7 ns; and best single-level transition total SETUP and HOLD times of about 0.9 ns and 1 ns
Keywords :
CMOS memory circuits; integrated memory circuits; multivalued logic circuits; HOLD clock mode; SETUP clock mode; memory circuits; multiple valued logic voltage signals; polysilicon-gate CMOS technology; voltage-mode CMOS multiple valued logic memory circuits; CMOS logic circuits; CMOS memory circuits; CMOS technology; Clocks; Latches; Logic circuits; Multivalued logic; Read only memory; Signal processing; Voltage;
Conference_Titel :
Multiple-Valued Logic, 1995. Proceedings., 25th International Symposium on
Conference_Location :
Bloomington, IN
Print_ISBN :
0-8186-7118-1
DOI :
10.1109/ISMVL.1995.513509
