On designing of 4-valued memory with double-gate TFT

Author

Lee, Chung Len ; Chern, Horng Nan ; Liao, Min Shung ; Wang, Hui Min

Author_Institution

Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan

fYear

1995

fDate

23-25 May 1995

Firstpage

187

Lastpage

192

Abstract

We propose and analyze a new 4 valued memory cell by using the double gate thin film transistor (TFT). First, the structure of the double gate TFT is introduced. An equivalent circuit of the double gate TFT is proposed for the HSPICE simulation. Two circuits which are composed of the resistor load and the CMOS load basic block circuit are proposed and analyzed. The simulation results by using a laboratory 5 μm technology show that the memory cell circuits use only 10 transistors, as compared to 12 transistors of a conventional 2 bit memory cell, but can store a higher density of information

Keywords

CMOS memory circuits; SPICE; SRAM chips; equivalent circuits; integrated circuit design; memory architecture; multivalued logic circuits; thin film transistors; 4 valued memory cell; 4-valued memory; CMOS load basic block circuit; HSPICE simulation; SRAM cell circuit; circuit design; double gate TFT; double gate thin film transistor; double-gate TFT; equivalent circuit; memory cell circuits; multivalued logic; resistor load; CMOS memory circuits; Circuit simulation; Circuit synthesis; Counting circuits; Equivalent circuits; Laboratories; Random access memory; Read only memory; Thin film transistors; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Multiple-Valued Logic, 1995. Proceedings., 25th International Symposium on

Conference_Location

Bloomington, IN

ISSN

0195-623X

Print_ISBN

0-8186-7118-1

Type

conf

DOI

10.1109/ISMVL.1995.513530

Filename

513530