Reducing hardware requirement in FIR filter design

A hardware optimization scheme based upon minimum-adder CSD multiplier blocks is combined with a technique for trading adders for delays to reduce hardware requirements for fixed-coefficient FIR filters well below that achieved with either technique alone. The technique starts with determining the minimum order filter necessary to meet the filter specifications assuming infinite precision filter coefficients. Then the coefficients are truncated to B bits (which may be specified by the designer) and the order of the filter is increased, if necessary, to meet the filter specifications. From this baseline filter, an exhaustive search is carried out by increasing the filter order (adding delays) and decreasing the bits (decreasing adders) to search for the minimum hardware. At each search point, the minimum-adder CSD multiplier block approach is used to assure the optimum hardware realization. The result is the implementation in FPGAs or VLSI of FIR filters with less real estate and/or with less power consumption