Title :
Wavelet packet transforms for system-on-chip applications
Author :
Masud, Shahid ; McCanny, John V.
Author_Institution :
DSiP Labs., Queen´´s Univ., Belfast, UK
Abstract :
A methodology for the production of silicon cores for wavelet packet decomposition has been developed. The scheme utilizes efficient scalable architectures for both orthonormal and biorthgonal wavelet transforms. The cores produced from these architectures can be readily scaled for any wavelet function and are easily configurable for any subband structure. The cores are fully parameterized in terms of wavelet choice and appropriate wordlengths. Designs produced are portable across a range of silicon foundries as well as FPGA and PLD technologies. A number of exemplar implementations have been produced
Keywords :
CMOS digital integrated circuits; channel bank filters; digital filters; field programmable gate arrays; programmable logic devices; wavelet transforms; CMOS ASIC libraries; FPGA technology; PLD technology; Si; biorthgonal wavelet transform; efficient scalable architectures; orthonormal wavelet transform; signal coding; silicon cores; silicon foundries; subband structure; system-on-chip applications; wavelet filter banks; wavelet function; wavelet packet decomposition; wavelet packet transforms; wordlengths; Filter bank; Frequency; Laboratories; Signal analysis; Silicon; Speech analysis; System-on-a-chip; Wavelet analysis; Wavelet packets; Wavelet transforms;
Conference_Titel :
Acoustics, Speech, and Signal Processing, 2000. ICASSP '00. Proceedings. 2000 IEEE International Conference on
Conference_Location :
Istanbul
Print_ISBN :
0-7803-6293-4
DOI :
10.1109/ICASSP.2000.860102
