Implementation of Coordinate Rotation Algorithm for Digital Phase Locked Loop System in In-Phase and Quadrature Channel Signal Processing

Digital Signal Processing (DSP) system involves a wide spectrum of DSP algorithms for its realization and is often accelerated by use of novel VLSI design techniques. Now-a-days various DSP systems are implemented on a variety of programmable signal processors or on application specific VLSI chips. Coordinate Rotation Digital Computer (CORDIC) algorithm has turned out to be widely researched topic in the field of vector rotated Digital Signal Processing (DSP) applications due to its simplicity. This paper presents the design of pipelined architecture for coordinate rotation algorithm for the computation of loop performance of complex Digital Phase Locked Loop (DPLL). The design of CORDIC in the vector rotation mode results in high system throughput due to its pipelined architecture where latency is reduced in each of the pipelined stage. Saving area on silicon substrate is essential to the design of any pipelined CORDIC. The area reduction in proposed design can be achieved through optimization in the number of micro rotations. For better loop performance of first order complex DPLL and to minimize quantization error, the number of iterations are also optimized.