Time-sharing architectures for FIR filter structures

Due to the still increasing gap between high clock rates which are technically feasible and essentially fixed sampling rates in many application domains time-sharing architectures are increasingly important. However, an efficient utilization of silicon resources cannot be achieved by a simple top-down approach for the mapping of sequential operations onto the same hardware. Rather the local topology of circuit design and layout has to be considered in order to maximize efficiency. Therefore modified bitplane architectures which provide exceptionally efficient silicon utilization due to the small synchronization overhead are used as a starting point. Several alternative time-sharing approaches have been elaborated in order to explore the possible choices for an adaptation to system requirements. A quantitative comparison for the most attractive architectures is provided which shows to what extent the advantages of modified bitplane architectures can be maintained. A typical example of a complex FIR filter serves as an illustration of the overhead of time-sharing architectures