VLSI Architecuture for Neural Network Based Image Compression

Image compression is one of the key image processing techniques in signal processing and communication systems. Compression of images leads to reduction of storage space and reduces transmission bandwidth and hence also the cost. Advances in VLSI technology are rapidly changing the technological needs of common man. One of the major technological domains that are directly related to mankind is image compression. Neural networks can be used for image compression. Neural network architectures have proven to be more reliable, robust, and programmable and offer better performance when compared with classical techniques. In this paper the main focus is to development of new architectures for hardware implementation of neural network based image compression optimizing area, power and speed as specific to ASIC implementation, and comparison with FPGA. The proposed architecture design is realized on ASIC using Synopsys tools targeting 130nm TSMC library. The ASIC implementation for 16 input neuron with low power techniques adopted such as buffer insertion, clock gating and power gating limits dynamic power in the range 449μW to 713μW, cell leakage power to 18μW to 28μW, total cell area from 6319 Sq μm to 8662 Sq μm with maximum frequency ranging from 80MHz to 120MHz. ASIC physical design reports, the total power to be 20.2574μW, 97% better than the power during synthesis. In ASIC Physical Design a chip size of 14334.07Sq μm is achieved out of which the core area is 9945.07Sq μm, and it requires 8 metal layers for routing total wire length of 12592.2μm.