Title :
Design methodology for a 1.0 GHz microprocessor
Author :
Posluszny, S. ; Aoki, N. ; Boerstler, D. ; Burns, Jack ; Dhong, S. ; Ghoshal, U. ; Hofstee, P. ; LaPotin, D. ; Lee, K. ; Meltzer, D. ; Ngo, H. ; Nowka, K. ; Silberman, J. ; Takahashi, O. ; Vo, I.
Author_Institution :
IBM Austin Res. Lab., Austin, TX, USA
Abstract :
This paper describes the design methodology used to build an experimental 1.0 GigaHertz PowerPC integer microprocessor at IBM´s Austin Research Laboratory. The high frequency requirements dictated the chip composition to be almost entirely custom macros using dynamic circuit techniques. The methodology presented will cover design and verification tools as well as circuit constraints and microarchitecture philosophy. The microarchitecture, circuits and tools were defined by the high frequency requirements of the processor as well as the aggressive design schedule and size of the design team
Keywords :
logic CAD; microprocessor chips; 1 GHz; 1.0 GHz microprocessor; PowerPC integer microprocessor; custom macros; design methodology; design schedule; dynamic circuit techniques; microarchitecture; Design methodology; Frequency; Latches; Logic circuits; Logic design; Microarchitecture; Microprocessors; Programmable logic arrays; Read only memory; Timing;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1998. ICCD '98. Proceedings. International Conference on
Conference_Location :
Austin, TX
Print_ISBN :
0-8186-9099-2
DOI :
10.1109/ICCD.1998.727018
