Design and Verification of Cache Memory Decoder for High Speed Multicore Processor

Multi-core processing is a growing industry trend as single core processors rapidly reach the physical limits of possible complexity and speed. In case of single core processors, the increased performance incurs the more heating and cooling arrangements, as heating is a consequence of power dissipation. The cache design in existing SMT and superscalar processors is optimized for latency, but not for bandwidth. The size of the L1 data cache did not scale over the Past decade. Instead, larger unified L2 and L3 caches were introduced. The present project is the part of the L3 cache. This paper describes last level cache memory decoding structure, which is designed mainly to improve the timing, reduce the power consumption and better performance. Functional verification as well as pre layout and post layout STA and ERC verifications are done on the 4MB cache. Results of each verification flow are presented. Based on the SDP methodology, good placement and routing, RC extraction, and noise analysis are achieved. SDP methodology is proven better than the RLS methodology for data path configurations. Intel Specific tools are used for performing the verification of SDP flows.