Title :
Efficient BIST TPG design and test set compaction for delay testing via input reduction
Author :
Chen, Chih-Ang ; Gupta, Sandeep K.
Author_Institution :
Equator Technol. Inc., Campbell, CA, USA
Abstract :
This paper describes an input reduction design framework for delay testing. This design framework can be used to construct efficient test pattern generators (TPGs) for built-in self-test (BIST), to order scan cells in a scan chain to eliminate unnecessary dummy flip-flops, and to generate compact test sets for delay testing
Keywords :
automatic test pattern generation; built-in self test; delays; logic design; logic testing; BIST TPG design; built-in self-test; compact test sets; delay testing; design framework; input reduction; scan cells; scan chain; test pattern generators; test set compaction; Built-in self-test; Circuit faults; Circuit testing; Clocks; Compaction; Delay; Fault detection; Flip-flops; System testing; Test pattern generators;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1998. ICCD '98. Proceedings. International Conference on
Conference_Location :
Austin, TX
Print_ISBN :
0-8186-9099-2
DOI :
10.1109/ICCD.1998.727020
